The present invention relates to a data processor having bus lines whereby data exchange is commonly performed among a plurality of inner circuits.
In a conventional data processor having such bus lines, a three-state buffer, which outputs high-impedance output states other than HIGH and LOW logical states, is provided for each of the inner circuits, and only one of the three-state buffer is permitted to exclusively drive the bus lines so that output data of more than one inner circuits may not collide on the bus lines.
FIG. 5 is a block diagram illustrating a partial configuration of a conventional data processor around the bus lines, wherein inner circuits of the data processor, such as an instruction processor, an instruction fetch unit, a cache memory or a main memory, are represented by inner circuts 11 to 15 connected to the bus lines.
In each of the inner circuits 11 to 15, a three-state buffer is provided, which connects output data of respective one of the inner circuits 11 to 15 to the bus lines time-divisionally, controlled with an output enable signal which is generated according to active status of a bus-usage permission signal supplied to the respective inner circuit from a bus controller 6 for permitting exclusive usage of the bus lines. The output data connected to the bus lines is supplied directly to every of the inner circuits 11 to 15 trough the bus lines.
The bus controller 6 takes charge of arbitrating usage of the bus lines according to bus-usage request signals received from the inner circuits 11 to 15 and enables one of bus-usage permission signals each connected to each of the inner circuits 11 to 15, respectively.
Each of the inner circuits 11 to 15 controls its three-state buffer by way of the output enable signal generated according to the bus-usage permission signal delivered from the bus controller 6, and the three-state buffer of the inner circuit whereof the bus-usage permission signal is enabled drives the bus lines of 32 signal lines, for example, exclusively. Thus, data exchange among the inner circuits 11 to 15 is performed commonly, making use of the bus lines.
However, in the conventional data processor, every one of the bus lines must be wired so as to connect with the three-state buffer of every one of the inner circuits. Therefore, the bus lines become inevitably long and their parasitic capacitance becomes large when the number of the inner circuits increases. The wiring widths are very narrow in the highly integrated circuit. Hence, the long bus lines bring high wiring resistance, which becomes a factor of transmission delay of the data exchanged by way of the bus lines, obstructing high-speed data transmission even when the bus lines are driven by transistors of high fan-out ability.
Furthermore, the outputs of every of the three-state buffers are directly connected to the bus lines, in the conventional data processor. Therefore, there may arise an overlap of different outputs from different three-state buffers, resulting in dissipation of useless current.
Still further, a pull-up or a pull-down circuit must be provided to each of the bus lines, for preventing them from being left floating when no three-state buffer drives the bus lines. Otherwise, the high-impedance of the bus lines may cause through current flowing through input gates of the three-state buffers.